(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the deep contact processing window in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, it is sometimes necessary to form a deep contact hole with deep submicron feature sizes and high aspect ratios; that is, a contact opening in which the ratio of height to width of the opening is much greater than one. High density plasma etchers must be used to form these deep contact holes. However, the low selectivity of photoresist to inter-layer dielectrics makes complete etching of the deep contact holes impossible. It is necessary to implement a hard mask in order to achieve complete etching. It is also necessary to provide a process that will result in clean etching of the deep contact holes without contaminants that will cause high contact resistance.
U.S. Pat. No. 5,330,879 to Dennison shows a method of fabricating close-tolerance lines in which a masking material is deposited within a void, following by chemical mechanical polishing (CMP), and then etching away all material except for the filled void and underlying layer to form the close-tolerance lines. U.S. Pat. Nos. 5,173,442 and 5,091,339 to Carey show methods of forming vias and channels in insulating layers using masks and CMP processes.